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ir3087pbf data sheet xphas e tm phase ic with opti-phas e tm , ovp, and overtem p detect des cript ion the ir308 7 phase ic co mbined with an ir xphase tm cont rol i c p r ovide s a full feature d and flexible way to impleme n t p o we r solution s for th e late st high pe rfo r man c e cpus an d asics. the ?cont rol? ic provid es overall sy ste m control and interface s wi th any numbe r of ?phase? ics which ea ch drive and monitor a si n g le pha se of a multipha se co n v erter. the xphase tm arch itecture re sult s in a power supply that is smaller, less expen sive, and ea sier to d e sig n while p r oviding hi gh e r efficien cy than co nventio nal app roa c h e s. the ir3 087 with o p ti- p has e tm is intend ed for ap plica t ions de mand ing increa se d efficiency un der me dium t o light load co ndition s. both gate drive r s will d r ive l o w at a p r o g ramm able o u tput cu rre nt threshold. t h is effectively disconn ect s the pha se from the load eli m i nating po wer losse s du e to switchin g and ci rcula t ing c u rrents . feat ure s ? 2.5a average gate drive current ? loss-le ss in ducto r cu rren t sense ? internal indu ctor dcr te m peratu r e com pen sation ? programma bl e phase dela y ? programma bl e feed -fo r ward voltag e mode pwm ramp ? sub 100n s mi nimum pulse width supp orts 1mhz pe r-pha se op erati on ? curre n t sense amplifier dri v es a si n g le wire average curre n t share bus ? curre n t share amplifier re duces p w m ra mp slop e to ensure sha r ing between pha se s ? body bra k in g tm disable s synchrono us mosfet for improv e d tran sient re sp on se and prevent s neg ative output voltag e at converte r turn-off ? opti-pha se tm redu ce s the n u mbe r of pha se s for imp r o v ed light to medium loa d efficien cy ? ovp comp arator with 15 0 n s re sp on se ? programma bl e phase over-temp e rature detectio n ? small thermal l y enhan ced 20l mlpq p a ckag e applicat ion circuit r p h ase 2 rcs + cc s - cv cc l rp ha s e 3 cv ccl cs co m p 20k rb ia s i n db s t rp ha s e 1 ccs + rv c c rp wm rm p cin rc s - cp wmrm p cb s t vo ra m p bi as da c vr h o t ea is ha re 12 v co vg at e 5 w i r e a n al og b u s fr om c o nt r o l i c da ci n 19 bi as i n 20 rm p i n + 1 rm p i n - 2 ga t e h 14 v cch 15 cs i n - 17 op t i ph s 18 ho t s e t 3 v rho t 4 sc om p 6 eai n 7 pg n d 13 gat e l 12 lgn d 9 p w mrmp 8 i s ha re 5 vc c 10 vc c l 11 cs in+ 16 ir 30 87 ph as e ic ro p 1 ro p 2 page 1 of 35 1 /31/05
ir3087pbf ordering information dev i c e o r d e r qu antit y IR3087MTRPBF 3000 p e r reel ir3087mpbf 100 pie c e stri ps absolute maximum ratings operating ju nction te mpe r ature?? ? ??..150 o c storage te m peratu r e ran ge?? ??? ??.-6 5 o c to 150 o c esd rating ???? ?? ???? ?? ??..hbm cl ass 1c jede c stan dard pin # pin name v ma x v mi n i sour ce i sink 1 r m p i n + 2 0 v - 0 . 3 v 1 m a 1 m a 2 r m p i n - 2 0 v - 0 . 3 v 1 m a 1 m a 3 h o t s e t 2 0 v - 0 . 3 v 1 m a 1 m a 4 v r h o t 2 0 v - 0 . 3 v 1 m a 3 0 m a 5 i s h a r e 2 0 v - 0 . 3 v 5 m a 5 m a 6 s c o m p 2 0 v - 0 . 3 v 1 m a 1 m a 7 e a i n 2 0 v - 0 . 3 v 1 m a 1 m a 8 p w m r m p 2 0 v - 0 . 3 v 1 m a 2 0 m a 9 l g n d n / a n / a 5 0 m a n / a 1 0 v c c 2 4 v - 0 . 3 v n / a 5 0 m a 11 vccl 27v -0.3v n/a 3a for 100n s, 200ma dc 12 gatel 27v -0.3v dc, -2 v for 100n s 3a for 100n s, 200ma dc 3a for 100n s, 200ma dc 13 pgnd 0.3v -0.3v 3a for 100n s, 200ma dc n/a 14 gateh 30v -0.3v dc, -2 v for 100n s 3a for 100n s, 200ma dc 3a for 100n s, 200ma dc 15 vcch 30v -0.3v n/a 3a for 100n s, 200ma dc 1 6 c s i n + 2 0 v - 0 . 3 v 1 m a 1 m a 1 7 c s i n - 2 0 v - 0 . 3 v 1 m a 1 m a 1 8 o p t i p h s 2 0 v - 0 . 3 v 1 m a 1 m a 1 9 d a c i n 2 0 v - 0 . 3 v 1 m a 1 m a 2 0 b i a s i n 2 0 v - 0 . 3 v 1 m a 1 m a page 2 of 35 1 /31/05
ir3087pbf electrical specifications unle ss otherwise sp ecifie d, thes e spe c ification s appl y over: 8.4v v cc 21v, 6v v cch 28v, 6v v ccl 14v, and 0 o c t j 125 o c, c gat e h = 3.3nf, c gat e l = 6.8nf par a mete r t e s t con d i t i o n m i n t y p m a x u n i t gate driv ers gateh ri se time vcch = 12v , measu r e 2v to 9v transitio n time 2 2 5 0 n s gateh fall time vcch = 12v, measu r e 9v to 2v transitio n time 2 2 5 0 n s gatel ri se time vccl = 12v, measu r e 2v to 9v transitio n time 5 0 7 5 n s gatel fall t i me vccl = 12v, measu r e 9v to 2v transitio n time 5 0 7 5 n s gatel low t o gateh hig h delay vcch = vccl = 12v, mea s ure the time from gatel falling to 1v to gateh ris i ng to 1v 1 0 2 5 5 0 n s gateh lo w to gatel hig h delay vcch = vccl = 12v, mea s ure the time from gateh falling to 1v t o gatel ris i ng to 1v 1 0 2 5 5 0 n s disable pull-do wn curren t force gate h or gatel = 2v with biasin = 0v 1 5 2 5 4 0 p a current sense amplifier csin+ bias current -0.5 -0.25 0 p a csin- bia s c u rr ent -1 -0.4 0 p a input offset voltage csin+ = csi n - = daci n. measure input refe rre d offset from dacin - 3 0 . 5 5 m v gain at t j = 2 5 o c 3 2 3 4 3 6 v / v gain at t j = 1 2 5 o c 2 7 2 9 3 1 v / v slew rate curre n t sense amplifier ou tput is an internal n ode. slew rate at the ishare pin will be set by the internal 10k ? resi sto r and a n y stray external cap a cit a nc e 1 2 . 5 v/ p s differential in put ran ge -20 100 mv comm on mo de input ra n ge 0 4 v rout at t j = 2 5 o c 7 . 9 1 0 . 5 1 3 . 1 k ? rout at t j = 1 2 5 o c 9 . 3 1 2 . 4 1 5 . 5 k ? ram p dis c h a rge clam p clamp volta g e force i(pwm r mp) = 500 p a. measu r e v(pwmrmp) ? v(daci n) - 1 0 5 2 0 m v clamp disch a rge cu rre nt 4 8 ma page 3 of 35 1 /31/05
ir3087pbf par a mete r t e s t con d i t i o n m i n t y p m a x u n i t r a mp comparat or input offset voltage 20 40 80 mv hysteresi s note 1 -10 0 10 mv rmpin + , rm pin- bias cur r e n t - 1 0 1 a propa gation delay vcch = 12v. measu r e tim e from rmpin inp u t (50mv ove r drive) to gatel tran si tion to <11v. 1 0 0 1 5 0 2 4 0 n s pwm comparator pwm comparator input offs et voltage - 5 5 1 5 m v eain & pwmrmp bias cur r e n t clamp a nd current share adjust off -1 -0.4 1 a propa gation delay vcch = 12v. measu r e tim e from pwmrmp input (50mv ov erd r ive) to gateh transition to < 11v. 7 0 1 5 0 n s comm on mo de input ra n ge exceedin g the comm on m ode inp u t rang e re sult s in 100% duty cycle 5 v share adjust error amplifier input offset voltage 10 20 30 mv input voltage rang e eain ? pwmrmp, note 1 -3.5 3.5 v pwmrmp adjust current 4 8 ma tran scon du c t a n c e i ( p w m r mp) = 3.5m a, not e 1 0.9 1.6 2.3 a/v scomp sou r ce/sink cu rre nt note 1 20 30 40 a scomp activation voltage amount sco m p must increase from its minimum voltage until the ramp slo pe adjust cu rren t equals = 10 a 6 0 1 5 0 3 0 0 m v pwmrmp min voltage i(pwm r mp) = 500 a 1 5 0 2 2 5 3 5 0 m v 0% du ty cy cl e co m p a r a t o r thre sh old vo ltage comp are to v(daci n) 86 88 92 % propa gation delay vccl = 12v. measu r e tim e from eain < 0.9 x v(da cin) (20 0 mv overd r ive) to gatel trans i tion to < 11v. note 1. 1 0 0 1 5 0 n s opti-ph ase tm compar ator thre sh old vo ltage vdacin = 0.8v, v(optiphs) = 0.2 5 v -5 35 75 mv thre sh old vo ltage vdacin = 0.8v, v(optiphs) = 1.0v -55 10 90 mv thre sh old vo ltage vdacin = 0.8v, v(optiphs) = 2.0v -135 -25 105 mv thre sh old vo ltage vdacin = 1.2v, v(optiphs) = 0.2 5 v -10 45 90 mv thre sh old vo ltage vdacin = 1.2v, v(optiphs) = 1.0v -55 25 105 mv thre sh old vo ltage vdacin = 1.2v, v(optiphs) = 2.0v -130 0 135 mv thre sh old vo ltage vdacin = 1.6v, v(optiphs) = 0.2 5 v -15 50 115 mv thre sh old vo ltage vdacin = 1.6v, v(optiphs) = 1.0v -50 40 120 mv thre sh old vo ltage vdacin = 1.6v, v(optiphs) = 2.0v -125 10 155 mv propa gation delay 200 ns optiphs bias cu rrent -1 -0.2 1 a disable com parato r th re shold v( biasin) ? v(optiphs) 100 400 750 mv page 4 of 35 1 /31/05
ir3087pbf par a mete r t e s t con d i t i o n m i n t y p m a x u n i t ovp comparator thre sh old vo ltage comp are to v(daci n) 100 125 160 mv propa gation delay vccl = 12v. measu r e tim e from csin > v(da cin) (200mv overd r ive) to gatel tran si tion to <11v. 1 5 0 2 5 0 n s gener a l vcc sup p ly curre n t 10 14 ma vccl su pply current 2.5 5 ma vcch suppl y current 4v v cch 14v 5.5 8 ma 1 4 v v cch 28v 6.5 10 ma biasin bias current -5 -2.5 2 p a dacin bia s cur r e n t -2 -1 1 p a vrho t com p arat or hotset bia s cu rr ent -6 -4 -2 p a output voltag e i(vrhot) = 2 9 ma 300 400 mv vrho t lea kage current v(vrhot ) = 5.5v 0 10 p a thre sh old hy stere s i s t j 85 o c 3 . 0 7 . 0 1 1 . 0 o c m i n t y p m a x thre sh old vo ltage t j 85 o c 4 . 7 3 m v / o c x t j + 1.36v 4.73mv/ o c x t j + 1.46v 4.73mv/ o c x t j + 1.56v v not e 1: gu a r antee d by de sign, but not tested in p r od uction page 5 of 35 1 /31/05
ir3087pbf pin des c ription pin# pin symbo l pin descri ption 1 rmpin+ non - inve rting input to ram p comp arator 2 rmpin- inverting inpu t to ramp co mparator 3 hotset inverting inpu t to vrhot compa r ator. conne ct re sist or divide r fro m vbias to lgnd to prog ram v r hot thre sh old. diod e or thermi stor ma y be sub s tituted for lower resi sto r for en han ced/remot e temperature sen s in g. 4 vrho t open colle ct or output of the vrhot co mpa r ator wh ich drive s lo w if ic junction temperature excee d s the us e r program mable limit. conne ct extern al pull-u p . 5 ishare output of the curre n t sense amplifier an d input to the share adju st erro r amplifie r. voltage on thi s pin is e qual to v(daci n) + 34 * [v(cs i n+) ? v(csi n -)]. conn ect i ng ishare pins together crea tes a share bus en abling current sh arin g betwe en ph ase ics. the sha r e bu s is al so used by the control ic for voltage positi oning a nd ov er- curre n t prote c tion. 6 scomp comp en satio n for the cu rrent share co ntrol loop. co nne ct a cap a c itor to groun d to set the co ntro l loop?s b and width. 7 eain pwm co mpa r ator input fro m the error a m plifier outp u t of control ic. both gate drive r output s drive lo w if the voltage on this pin is le ss than 88% of v(daci n). 8 pwmrmp pwm co mpa r ator ra mp inp u t. conne ct a re si stor from this pin to the converte r inp u t voltage and a capa citor to lgnd to pro g ram the p w m ramp. 9 lgnd signal groun d and ic sub s trate conn ection 10 vcc powe r for internal circuitry 11 vccl powe r for lo w-sid e gate driv e r 12 gatel low-side g a te drive r outp ut and input to gateh no n-ove r lap co mparator 13 pgnd return for gate drivers 14 gateh high -side g a te driver o u tput and inp u t to gatel no n-ove r lap co mparator 15 vcc h powe r for hig h -side g a te driv e r 16 csin+ non - inve rting input to the curre n t sense amplifier 17 csin- inverting inpu t to the curre nt sens e am plifier and n o n -inve r ting in put to the ovp comp arator 18 optiphs input to the opti-pha se tm comp arator. if the voltage on this pin ex cee d s the vol t age on the ishare pin minus t he voltage on t he dacin pi n the gatex pins will d r ive low. co nne ct external resi stor divider to biasin, opt i phs and lg nd to progra m , or co nne ct to biasin to disable. 19 dacin referen c e vo ltage input fro m the control ic and also inverting inp u t to the ovp comp arator. curre n t sen s i ng and pwm operation referen c e d to this pin. 20 biasin system reference voltage for intern al circuitry page 6 of 35 1 /31/05
ir3087pbf syst em theory of operat ion xphase tm ar chitec ture the xphas e tm architectu re is de signe d for multipha se interle a ved buck convert e rs whi c h a r e used i n appl ication s requi rin g sm all si ze, de si gn flexibility, low voltage, high cu rrent and fa st tran sient respon se. the a r chitecture ca n control converters of any pha se number where flexibility fa cilitates the desi gn trade-off of multiphase converters. the scala b le architectu re can be ap plied to other appli c ation s which requi re hig h curre n t or mu ltiple output voltage s. as sho w n i n figure 1, th e xphase tm archite c ture co nsi s ts of a control i c a nd a scal able array of ph ase converte rs each usin g a single pha s e ic. the co ntrol ic com m unicates with the phase ics throug h a 5-wire anal o g bus, i.e. bias voltage, pha se timin g , avera ge cu rr ent, erro r am plifier o u tput, and vid volta ge. th e cont rol ic in co rpo r ates al l the system functio n s, i.e. vid, pwm ramp oscillato r, erro r ampli f ier, bias voltage, and faul t protection s etc. th e phase i c imp l ements th e functio n s req u i r ed by the co nverter of e a c h ph ase, i. e. the gate driv ers, p w m co mparator and latch, over-volta ge protection, an d curre n t sen s i ng and sha r in g. there is no unu sed o r re dund ant silicon with the xphase tm archite c ture co mpared to others su ch a s a 4 phase controlle r tha t can be con f igured for 2, 3, or 4 ph a s e o p e r ation. pcb layo u t is e a si er sin c e the 5 wire bu s eliminate s the need for p o int-to-point wirin g betwe en the control ic and ea ch pha s e. the criti c al ga te drive an d curre n t sen s e conn ectio n s are sho r t and local to the phas e ics. this improv es the pcb layout by lowering th e para s itic in du ctan ce of the gate drive ci rcuits a nd re d u cin g the noi se of the cu rrent sen s e sig nal. 0. 1uf cc s rcs cc s 0. 1uf cin rcs vou t + vou t - vou t sen s e - vi d 0 vi d 3 12 v vou t sen s e + vi d 4 vi d 2 vr h o t pow e r goo d vi d 5 vi d 1 en a b le oc i n p u t /out p u t a ddit iona l p hase s << current sense >> pwm con trol >> phase t iming >> bias vo ltage ir 3081a co ntrol ic >> vid vol tage c urrent s hare c urrent s hare co ut c ontro l b u s ir30 87 phas e ic b ias volt age gate volt age regu lator ir30 87 phas e ic p hase hot p hase hot p hase fau lt v id volta ge p wm contr ol p hase tim ing b ias volt age v id volta ge p wm contr ol p hase tim ing oc oc oc oc oc oc oc oc figure 1. system block di agra m page 7 of 35 1 /31/05
ir3087pbf pwm con t ro l method the pwm blo ck diag ram of the xphase tm architectu re is sho w n in f i gure 2. fee d - forward volta ge mo de cont rol with trailing ed ge modulatio n is used. a high -gain wide -ba ndwi d th voltage type error amplifier in the co ntrol ic is use d for the voltag e cont rol loo p . an external rc circuit co nne ct ed to th e input voltag e and g r ou nd is used to progra m the slop e of the pwm ram p and to provide the feed-forward co ntrol at each ph ase. the pwm ramp slope will chang e with the in put voltage an d automatically comp en sate f o r chan ge s in the input volt age. th e inp u t voltage ca n ch ang e due to vari ations i n the sil v er box outp u t voltage or due to the wi re an d pcb - trace voltage drop rel a ted to ch ang e s in load curren t. + - 10 k + - sh ar e ad ju s t er ro r a m p lif ie r cur re nt sen se amp li fie r x34 x 0 .91 2 0mv + - + - + - 10 k sh ar e ad ju s t er ro r a m p lif ie r cur re nt sen se amp li fie r x34 2 0mv x 0 .91 + - + - + - + - + - da ci n p w mr mp bi as i n ra m p i n - ra m p i n + ga t e h sc o m p i s ha re cs in + ga t e l ea i n cs i n - sy st em re fe ren ce vo lt age enab le clo ck pul se gen er ato r body brak ing comp arat or ram p dis ch arg e cla mp pw m la tc h s res et domin ant ph as e ic r pw m c omp ar ato r r drp rp w m rm p rp hs 2 cs co m p + - rp hs 1 + - + - rcs rv f b + - cp w m rm p cs co m p cc s rp w m rm p rcs + - cp w m rm p + - + - cc s rp hs 2 rp hs 1 + - gn d vo u t bi as i n vd ac vb i a s da ci n p w mr mp ra m p i n + vo s n s- vo s n s+ v o sn s- i s ha re ra m p i n - ii n vd r p ea i n ga t e h sc o m p cs i n - cs in + ga t e l ea o u t rm p o ut vi n fb ir os c sy st em re fe ren ce vo lt age vda c body brak ing comp arat or ram p dis ch arg e cla mp enab le clo ck pul se gen er ato r v bia s r egu la tor if b vdr p amp 50% dut y cyc le ra m p g e ne ra t o r vva lley vpe ak e rro r am p r s res et domin ant pw m la tc h ph as e ic cout co nt rol i c pw m c omp ar ato r figure 2. pwm block diag ram freque nc y a nd phase ti ming contro l an oscillator with program m able frequency is located in the control ic. t he ou tput of the oscill ator i s a 50% duty cycle tria ngle waveform wi th peak a nd valley voltages of app roxi mately 4.6v and 0.9v re spectively. this sig nal is use d to pro g ram both the swit chin g fre quen cy and p hase ti ming o f the phase i c s. th e pha s e ic is p r og ra mmed by resi sto r divider r phs1 and r phs2 conn ected b e twee n the vbias referen c e voltage and the phase ic l g nd pin. a comp arator i n the phase ics dete c ts t he crossin g of the oscilla tor wavefo rm over the voltage gene rat ed by the resi sto r divid e r a nd t r igg e rs a cl ock pul se that start s t he p w m cycl e. the pea k and vall ey vol t ages tra c k th e vbias voltage re du cing pote n tial phase i c timi ng erro rs. fi g u re 3 sh ows t he pha s e tim i ng for a n 8 p hase convert e r. note that both sl op es of the t r ian g le waveform can be u s e d for pha se timi ng by swa ppi ng the rmpin+ and rmpi n? pi ns, as sho w n in figure 2. page 8 of 35 1 /31/05
ir3087pbf ramp (from control ic) clk 1 vva ll ey (1 .0 0v) phase ic clock pulses vph as e1& 8 (1 .5v ) vph as e3& 6 (3 .5v ) vph as e2& 7 (2 .5v ) vph as e4& 5 (4 .5v ) vpe ak (5 .0 v) clk 2 50 % r a m p du ty cy cle clk 3 clk 4 clk 5 clk 6 clk 7 clk 8 sl op e = 8 0mv / % dc sl op e = 1 .6m v / ns @ 200 kh z sl op e = 8 .0m v / ns @ 1mh z figure 3. 8 phase oscillat o r waveform s pwm oper ation the p w m co mparator i s lo cated in the phase ic. upo n re ceivin g a clo c k pul se, t he pwm latch is set; the p w m r m p voltage begi ns to increase; the low side driver i s turned off, and the high side dri v er is then turned on after the non- overlap time. when the p w m r mp voltage exceed s the error a m plifier? s out put voltage, the pwm latch is re set. this turns off the high sid e driver an d then turn s on the lo w sid e driver after th e non-overla p time; it activates the ramp di scha rge cla m p, which qui ckly discha rge s th e pw m r mp cap a cito r to t he vda c vol t age of th e control i c until the next clo ck p u lse. the pwm lat c h is reset dominant allo wi ng all pha se s to go to zero duty cycle wi thin a few tens of nano se cond s in respon se to a load step decrea s e. ph ase s can overlap and go to 100% d u ty cycle in re spo n se to a load ste p increa se with turn -on gate d by the clo c k pul se s. an erro r amplifie r outp u t volta ge g r eate r th an the co mm on mo de input range o f the pwm compa r ator re sults i n 10 0 % duty cycle reg a rdl e ss o f the voltage of the pwm ramp. thi s arrang ement guarantee s the erro r amp lifier is always in cont rol a nd ca n dema nd 0 to 100% duty cycle as req u ire d . i t also f a v o r s re sp on se t o a loa d st ep d e cr ea se w h ic h is a ppropri a te given the low o u tput t o inp u t voltag e ratio of most sy stems. the inducto r current will in cre a se mu ch more rapidly than de crea se in resp on se to load tran sie n ts. this control method is de sign ed to p r o v ide ?sin gle cycle tran sient re sp on se? where the ind u c tor current chang es in respon se to l oad tra n sie n t s within a si ngle switchin g cycle m a ximizing th e effectivene ss o f the powe r train a n d minimizi ng th e output capa citor requi re ments. an ad ditional adva n tage is th at differen c e s in grou nd o r in put voltage at the phases have no effect on ope ratio n sin c e the pwm ra mp s are referen c ed to vdac. figure 4 depi cts pwm o p e r ating wavefo rms u nde r variou s co nditio n s. page 9 of 35 1 /31/05
ir3087pbf ph ase i c cl ock pu lse eai n vda c pw mrm p ga teh ga tel st ea dy- st at e op er ati on du ty cy cl e i n c rea se du e to lo ad in cr eas e dut y cyc le de cr ea se due t o v i n in cr ea se (fe ed -fo rw ard ) du ty cy cle d ecr ea se du e to lo ad de cre as e ( b o dy br ak ing ) or fa ult (v cc uv , v c c vid u v , oc p, vi d= 111 11 x) st ea dy- st at e op er ati on 91 % v d a c figure 4. pwm operating wavefo rms body braking tm in a conventi onal syn c h r o nou s buck co nver ter, the minimum time requi red to redu ce the current in the indu ctor in respon se to a load step d e c re ase is; o min max slew v i i l t ) ( * ? = the sl ew rate of the ind u ctor cu rrent can be sig n i ficantly incre a se d by turn ing off the synchrono us rectifier in respon se to a loa d step decrea s e. th e switch n o d e vo ltage is then fo rced t o de cr ea se until cond ucti on of th e synchro nou s re ctifier?s bo dy diode occu rs. t h is i n creases th e vo ltage a c ro ss the indu ctor from vout to vout + v bod y di ode . the minimu m time requi red to re du ce the cu rre nt in the inductor in re spo n s e to a loa d transi ent decrea s e i s n o w; bodydiode o min max slew v v i i l t + ? = ) ( * since th e vol t age d r op i n t he bo dy dio d e is often hi g her th an o u tp ut voltage, th e indu cto r cu rre nt sle w rat e can be increa sed by 2x or more. this patent pendi ng te ch nique i s refe rre d to a s ?b ody braki ng? and i s a c co mplish e d throug h the ?0% duty cy cl e co mpa r ato r ? lo cated i n th e ph a s e ic. if the error a m plifier?s outp u t voltage drop s bel ow 88% of the vdac voltage this co mpa r at or turn s off the low si de gat e driver. lossles s av erage indu ctor curre nt s e nsing inducto r cu rrent can be se nse d by conn ecting a resi stor and a cap a citor in p a ral l el with the inducto r and m easurin g the voltage a c ro ss the cap a citor, a s sho w n in figu re 5. the equati on of the sen s ing n e two r k i s , cs cs l l cs cs l c c sr sl r s i c sr s v s v + + = + = 1 ) ( 1 1 ) ( ) ( usually the resi stor rcs a nd capa citor ccs a r e cho s en so that th e time con s tant of rcs a nd ccs eq ual s the tim e con s tant of th e ind u cto r wh ich i s th e ind u ctan ce l over the ind u ct or dcr (r l ). if the two time cons tants matc h, the voltage a c ro ss ccs is prop ortional to th e cu rrent thro ugh l, a nd th e se nse ci rcu i t can b e tre a t ed as if o n ly a se nse resi sto r with the value of r l was u s ed . the mi smat ch of the tim e const ants doe s not affect the m e a s u r eme n t of indu ctor dc current, but affects the a c compon ent of the indu ctor current. page 1 0 of 35 1 /31/05
ir3087pbf v l l r l i v l o r c cs cs c o cu rren t v s c c sense a m p csout figure 5. inductor cu rre nt sens in g and curre n t sense amplifier the advanta ge of sen s in g the indu cto r cu rre nt versu s high side or low si de sen s in g is th at actual out put curre n t being delive r ed to the load is obtaine d rather than pea k or sa m p led inform ation about the switch cu rre nts. the output voltag e ca n be po si tioned to m e et a load line based o n re al time inform ation. except for a sen s e resi stor i n seri es with indu ctor, this is the only sen s e meth o d t hat can suppo rt a sin g le cycle tra n sie n t respo n se. othe r method s provide no inform ation duri ng e i t her load in crease (lo w sid e sen s in g) o r load de crea se (high side sensi ng). an additional proble m associate d with pea k or valle y current mo de co ntrol for voltage posit ioning i s that they suffer from pea k-to -averag e erro rs. the s e e r rors will sh ow in many wa ys but one e x ample is th e effect of freque ncy variation. if the freq uen cy of a particul a r unit is 10 % low, the p eak to p e a k indu ctor curre n t will be 10 % large r and the output im peda nce of the c onverte r will drop by about 1 0 %. variation s in indu ctan ce, current sen s e amplifie r band width, p w m pro p d e l a y, any ad de d sl ope com pen sa tion, i n put voltage, and output v o ltage are all additio nal sou r ces of pe ak-to - ave r ag e errors. current sense amplifier this i s a hig h speed diffe rential cu rren t sen s e ampli f ier, as sho w n in fi gure 5. its gain de creases with i n cre a si ng temperature and is n o mi nally 34 at 25oc and 2 9 at 125oc (-1470 p p m/oc). this redu ction of gain tends to comp en sate t he 3 850 ppm /oc in crea se i n ind u cto r dcr. si n c e in most de sign s the ph ase i c ju nctio n i s hotter th an the ind u cto r t hese two effe cts te nd to cancel su ch th at no additio nal temp erature co mpe n sation of th e l oad li ne i s requi re d. the cu rrent sen s e amplifi e r ca n a c cep t positive differ ential inp u t up to 1 00m v and ne gati v e up to -20 m v befo r e clippi ng. the output of the curre n t se nse amplifier i s su mmed with the da c volta ge and se nt to the co ntrol ic and other pha s e s throug h an o n -chip 1 0 k ? resi sto r co nn ected to the i s hare pi n. the ishare pins of all the phase s are tied to get her an d the voltage on t he sha r e bu s re pre s ent s th e averag e cu rrent bei ng deli v ered to the l oad and i s use d by the control ic for voltage pos iti oning a nd current limit prot ection. av erage cur r ent shar e l oop curre n t sh ari ng bet wee n p hases of the conve r ter i s a c hiev e d by th e avera ge cu rre nt sh are l o op in e a ch phase ic. the o u tput of the current sense am plifie r is compa r ed with the share bu s le ss a 20mv offset. if current in a pha se i s smalle r than the averag e curre n t, the share a d ju st erro r am plifie r of the phase will activate a curre n t sou r ce tha t redu ce s the slope of its pwm ra mp the r eby incre a si ng its duty cycle an d outpu t current. the cro s sover fre quen cy of the curre n t share lo op ca n be pro g ra mmed with a capa cito r at the scomp pin so that the sh are lo o p doe s not intera ct with the output voltage loo p . page 1 1 of 35 1 /31/05
ir3087pbf ir3087 theory of operati o n block diagra m the block dia g ram of the ir30 87 is sho w n in figu re 6, and sp ecifi c features a r e discusse d in the followin g se ction s . vdac ishare opti-phase disable comparator + - + - 400mv + - + - 10k + - + - + - + - + - + - + - + - + - + - + - + - + - rmpin+ vcc eain rmpin- scomp pwmrmp ishare gateh lgnd biasin pgnd vcch vccl csin+ gatel optiphs vrhot hotset csin- dacin internal c i r c u i t bias share adjust e r r o r a m p clock pulse generator ramp comparator 20mv ramp slope adjust pwm comparator reset pwm latch r s dominant s y s t e m r e f e r e n c e voltage 0% duty cycle comparator current sense amp gate non-overlap comparators x 0.88 ovp comparator 2v x34 voltage proportional to absolute temperature ramp discharge clamp enable vrhot comparator 125mv opti-phase comparator biasin vcc enable vdac vdac + + - + scomp figure 6. ir3087 block di agra m tri-sta t e ga te driv ers the gate driv ers can d e liver up to 3a pea k cu rre nt. an adaptive non-ove r lap circuit monito rs the voltag e on the gateh an d gatel pin s to prevent mo sfet shoot -throu gh curre n t while mini mizing b ody diode con d u c tion. an enable si gnal is p r ovid ed by the co ntrol ic to the p hase ic without the addition of a dedicate d sign a l line. the erro r amplifie r o u tput of th e control ic drives lo w in respon se to any fault con d ition su ch a s in put u nde r voltage or output ove r lo ad. the i r 30 87 0% d u ty cycle comp ara t or dete c ts thi s an d d r ives both gate out puts lo w. thi s tri-stat e operation p r e v ents neg ative indu ctor current and n e g a tive output voltage du ring power-do w n. the gate dri v ers revert to a high impe dan ce ?off? st ate if vccl and vcch supply voltage s are b e low t he norm a l operating ra nge. an 80 k ? re sisto r i s co nne cted across the gate h/gat e l and pg nd pin s to prevent th e gateh/gat e l voltage from risi ng du e to leakag e or other cause unde r these condition s. ov er voltage protec tion (ovp) the i r 308 7 i n clu d e s ove r -voltage p r ote c tion th at turn s o n th e lo w side mosfe t to p r ote c t the lo ad i n the event of a sho r ted hi gh-side m o sfet or conn ecti on of the co nverte r o u tpu t to an excessive out put v o ltage. a co mparato r monitors the voltage at th e csin- pin whi c h i s u s u a lly con n e c te d dire ctly to the converte r output. if the voltage excee d s the dacin volta ge pl us 125 mv typical (1 00mv mini m u m an d 1 6 0 m v maximu m), the gat e l pin drive s high. the o vp circuit overri de s the n o rmal p w m operation a n d will fully turn-on the l o w si de mos f et within approximatel y 150ns. the low si de mo sfet will re main on u n til the over-volt age conditio n cea s e s . page 1 2 of 35 1 /31/05
ir3087pbf whe n d e sig n i ng for ovp t he ove r all sy stem m u st be co nsi dered. i n many ca se s the ove r-cu rre nt protecti on of th e ac-dc o r dc-dc co nvert e r supplying t he multipha se conve r ter will be trigge re d thus p r ovidi ng effective p r otectio n without d a ma ge a s lon g a s all pcb tra c es a nd com p onent s a r e si zed to han dle the wo rst-ca se m a ximum curre n t. if this is not p o ssi ble a fuse can be adde d in the in put supply to the multipha se converte r. on e scen ari o to be careful of is whe r e the input voltage to the multipha se co nverter may be pulled belo w the level whe r e the ics ca n provid e adeq uate voltage to the lo w sid e mosf et thus defe a ting ovp. dynami c ch a nge s in the vid code to a lowe r output volt age may trigge r ovp. for exampl e; a 250mv decre ase in output voltage combi ned with a light load con d ition will cau s e th e low sid e mosfets to turn on an d in terfere with body bra k ing tm . this will not cause a problem , however, as body braki n g tm will re sum e o n ce the output voltage i s less than 12 5 m v above the vid voltage. since csin- pin is al so u s ed a s the i n ducto r cu rre n t sen s in g inp u t, it is u s ual ly con nect ed to the lo cal converte r output, which may b e fa r a w ay fro m the loa d of the multip h a se converte r. exce ssive distri bution impeda nce betwe en the conve r ter an d load may trigger ovp duri ng norma l op eration. if the voltage drop across the di stributio n impeda nce e x ceed s the m i nimum ovp comp arator t h re shol d of 1 00mv plu s vi d offset and voltage po siti oning, the ir308 7 ca n n o t be use d . the ir30 88a phase i c wit hout ovp sh ould be u s e d instea d in ap plicatio ns with exce ssive distribution i m pedance and very small or no avp. f o r exam ple, a converter having 25mv of vid offset, 125mv of avp at full load, and 100m v of drop in t he di stribution path at full l oad would be ok, since 100m v + 25mv + 125mv = 250mv whi c h i s greater than the 10 0mv drop. however, a converter havi ng 25mv of vid offset, no avp, and 130mv of drop in the di stribution path woul d re qui re ir 30 88a, since 100 mv + 25 mv + 0 m v = 1 25mv whi c h i s smalle r than t he 130mv d r op. conve r ter wit h high er o u tp ut voltage tha n vid voltage may also t r ig ger ovp d u ri ng no rmal o p e ration, a nd i r 30 88a sho u ld be u s ed to repla c e ir308 7. thermal mo nitoring (v rhot ) the ir3 087 senses it s o w n die temp erature a nd p r o duces a volta ge at the in p u t of the vrhot com p a r ator that i s prop ortio nal to temperatu r e. an external resi stor di vi der conn ecte d from vbias to the hotset pin and ground can be u s e d to p r ogra m the th ermal trip poi nt of the v r ho t co mpa r ator. th e vrhot pin i s a n op en-coll ector outp u t and sh ould b e pulle d u p t o a voltag e source th ro ug h a re sisto r . if the therm a l trip p o int i s rea c he d the vrhot output drive s low. opti-ph ase tm the numb e r of pha se s ch ose n fo r a p a r ticula r de sig n is b a sed up on m eeting therm a l req u irements a nd minimizi ng the numbe r of input and output ca pa ci to rs at the m a ximum outp u t current. at current s less than the m a ximum efficien cy will increase if less pha se s are u s ed. tu rni ng off ph a s e s as the o u tput cu rre nt decrea s e s i n crea se s efficien cy by eliminating the gate ch a r ging lo sse s , mosf et switchi ng lo sses, and circulating curre n ts in the mosfets a nd outp u t ind u ctors. f o r e a ch uniq ue d e sig n the r e will be an op timal point were pha se s should be turned off, one after another, to achieve the maximu m efficiency over the entir e output current range. the ir3 087 i m pleme n ts p a tent pendi n g opti-pha se tm control all o win g pro g ra mmable shut down of pha se s as a function of co nverter o u tpu t current. the opti-pha se tm comparato r monitors the voltage on th e ishare pi n less the voltage on th e dacin pi n. this voltage provide s a d i rect i ndi catio n of converte r output cu rrent. a resisto r divide r con n e c ted b e twee n the biasin, optiphs, and lgnd pins pro g ra ms t he threshold of the opt i -pha se tm comparator. i f the converte r output current drops below the programmed level the gate h and gatel pi ns will both drive lo w turn ing off the mosfets a nd cau s in g the i ndu ct or curre n t to begin to decay. the o u tput voltage will begi n to sag ca usi n g the control ic to immedi ately increa se t he duty cycle of the re m a ining pha se (s) to co mpen sate. th e voltage on th e ishare wil l remai n co nst ant as it re prese n ts the co nverter out pu t current rath er than th e current i n the individual pha se s. opti-pha se tm can be disab l ed by con n e c ting the opt i phs pin to the biasin pin. this mu st be don e on at least one pha se ic pe r conve r ter to e n su re op eration und er zero load conditi ons. page 1 3 of 35 1 /31/05
ir3087pbf applications information db s t qg at e rc s + ccs - ci n cp w m rm p cp w m rm p rcs - cv cc cv cc rc s + rp ha s e 3 3 cv c c l rc s + l cc p 1 rp ha s e 6 2 cv c c l rcs - db s t rc s + cfb cs c o m p db s t rp w m rm p cv cc cb s t cv c c l ccs - rp w m rm p cv c c l cc s + cv cc rc s + rp w m rm p 20 k rb i a s i n rc s + rp ha s e 5 3 rg a t e cc s + ci n ci n cs c o m p rp h a s e 1 3 rcp rp w m rm p rp ha s e 1 2 rp h a s e 6 3 cv da c cs c o m p r b b drp l ccs - ccp l cv c c l rcs - rv cc rp w m rm p cs c o m p rcs - rv da c vr h o t p o w e r g ood vo u t s e n se- vo u t s e n se+ vo u t + e n abl e vo u t - vi d 4 vi d 0 vi d 5 vi d 2 vi d 1 vi d 3 12v di st ri bu ti on im pe da nc e co ut da ci n 19 bi a s i n 20 rm p i n + 1 rm p i n - 2 ga t e h 14 vc c h 15 cs i n - 17 op t i ph s 18 ho t s e t 3 v rho t 4 sc om p 6 ea i n 7 pg n d 13 ga t e l 12 lg n d 9 p w mrmp 8 is h a r e 5 vc c 10 vc c l 11 cs i n + 16 ir3087 phase ic ro p 2 1 ro p 2 2 da c i n 19 b i asi n 20 rm p i n + 1 rm p i n - 2 ga t e h 14 vc c h 15 cs i n - 17 op t i ph s 18 ho t s e t 3 v rho t 4 sc o m p 6 ea i n 7 pg n d 13 ga t e l 12 lg n d 9 pw m r m p 8 is h a r e 5 vc c 10 vc c l 11 cs i n + 16 ir3087 phase ic ro p 3 1 ro p 3 2 da c i n 19 bi as i n 20 rm p i n + 1 rm p i n - 2 ga t e h 14 vc c h 15 cs i n - 17 opt i ph s 18 ho t s e t 3 v rho t 4 sc om p 6 ea i n 7 pg n d 13 ga t e l 12 lg n d 9 pw m r m p 8 is h a r e 5 vc c 10 vc c l 11 cs i n + 16 ir3087 phase ic ro p 5 1 ro p 5 2 da ci n 19 bi as i n 20 rm p i n + 1 rm p i n - 2 ga t e h 14 vc c h 15 cs i n - 17 op t i ph s 18 ho t s e t 3 v rho t 4 sc o m p 6 ea i n 7 pg n d 13 ga t e l 12 lg n d 9 pw m r m p 8 is h a r e 5 vc c 10 vc c l 11 cs i n + 16 ir3087 phase ic da ci n 19 bi as i n 20 rm p i n + 1 rm p i n - 2 ga t e h 14 vc c h 15 cs i n - 17 op t i ph s 18 ho t s e t 3 v rho t 4 sc o m p 6 eai n 7 pg n d 13 ga t e l 12 lg n d 9 p w mr mp 8 is h a r e 5 vc c 10 vc c l 11 cs i n + 16 ir3087 phase ic da ci n 19 bi as i n 20 rm p i n + 1 rm p i n - 2 ga t e h 14 vc c h 15 cs i n - 17 op t i ph s 18 ho t s e t 3 v rho t 4 sc om p 6 ea i n 7 pg n d 13 ga t e l 12 lg n d 9 p w mr mp 8 is h a r e 5 vc c 10 vc c l 11 cs i n + 16 ir3087 phase ic ro p 4 1 ro p 4 2 vg a t e l rp ha s e 1 1 cb s t 0. 1 u f rfb 1 cc s + db s t ro c s e t r drp 1 c ss/ d e l cs c o m p rb b f b cb s t 20 k rb i a s i n dg a t e r p h ase 43 cp w m r m p cv cc cdr p rp h a s e 2 1 cp w m r m p 20 k rb i a s i n 10 o h m rv cc 20 k rb i a s i n r drp rv cc rcs - cc s + rcs - cc s + cb s t rp w m rm p cp w m rmp ci n cb s t ccs - ci n ro p 6 1 rv cc 20 k rb i a s i n ro p 6 2 cp w m r m p 20 k rb i a s i n rc s + rf b rv cc cv cc rp h a s e 2 3 ccs - rp ha s e 4 1 cs c o m p cv c c l db s t rp h a s e 3 2 cc s + rp h a s e 2 2 ccs - cb s t ci n l l rv cc rc s + rp h a s e 5 2 ro s c db s t rp h a s e 5 1 rp h a s e 3 1 rv cc rp ha s e 4 2 rp ha s e 6 1 o s cds 1 vi d 5 2 vi d 0 3 vi d 1 4 vi d 2 5 vi d 3 6 vi d 4 7 pw r g d 26 tr m 1 8 tr m 2 9 vo sn s- 10 tr m 3 11 tr m 4 12 vd ac 14 ss / d el 25 ro s c 13 en a b l e 28 rm p o u t 24 lg n d 23 vc c 22 vb i a s 21 bb f b 20 ea o u t 19 18 fb vd r p 17 iin 16 oc s e t 15 n/ c 27 ir3081a control ic rs ha r e 0. 1u f cv cc page 1 4 of 35 1 /31/05 figure 7. 6 phase ir30 81 a/ 3087 vrm / evrd 10 converte r
ir3087pbf design procedures - ir3081a and ir3087 chipset ir308 1a ex tern al co mpone n ts oscillator resistor ros c the oscillato r of ir3081a gene rate s a t r iangl e wavef o rm to synchronize the ph a s e i c s, an d t he swit chin g f r equ en c y of the ea ch p hase conve r ter e qual s the oscillato r fr e quen cy, whi c h is set by th e extern al resistor r os c according t o the curve in f i gure 1 3 . soft sta r t c a pacitor c ss/ del b e cau s e t h e cap a cit o r c ss / d e l prog ra ms fou r different time pa ra meters, i.e. soft s t art delay time, s o ft s t art time, over-cu r rent l a tch d e lay ti me, and po wer g ood dela y time, they sho u ld b e co nsid ere d tog e ther whil e choo sing c ss/del . the ss/del pin voltage control s the sl ew rate of th e conv erte r o u tput voltage, as sho w n in figu re 10. a fter the enable pin voltage ri se s above 0.6v, t here is a soft-start d e lay time t ssdel, af ter which the error amplifie r outp u t is releas ed to allow the soft s t art. the s o ft s t art time t ss rep r e s ent s the time during whi c h convert e r voltage ri ses fro m z e ro to v o. t ss can be p r o g r amme d by an external ca pacito r , whi c h is determi ne d by equation (1). o ss o ss chg del ss v t v t i c * 10 * 70 * 6 / ? = = (1) once c ss/de l is cho s en, the soft start delay time t ssdel, the over-cu r rent fau l t latch delay time t ocdel , and the delay time t v ccpg from out put voltage (v o ) in re gula t ion to po we r goo d a r e fix ed a nd sh own in eq uation s (2), (3 ) and (4 ) re sp e c tively. 6 / / 10 * 70 3 . 1 * 3 . 1 * ? = = del ss chg del ss ssdel c i c t (2) 6 / / 10 * 40 115 . 0 * 115 . 0 * ? = = del ss ocdischg del ss ocdel c i c t (3) 6 / / 10 * 70 ) 3 . 1 735 . 3 ( * ) 3 . 1 065 . 0 8 . 3 ( * ? ? ? = ? ? ? = o del ss chg o del ss vccpg v c i v c t (4) vdac sle w rate progra mming capa citor c vdac and re sisto r r vdac the sl ew rat e of vdac d o wn -sl ope s r down can be programm ed by t he external ca pa citor c vdac a s defined in equation (5), whe r e i sink is the sin k current of vdac pin a s sh own in fi gure 15. the re sisto r r vdac is used to comp en sate vdac circuit and i s determ i ned by equa tion (6 ). t he sle w rate of v d ac up -sl o p e sr up i s pro portion a l to that of vdac do wn -sl o pe an d i s giv en by eq uation (7), whe r e i source is the sou r ce current of v d ac pin a s s h ow n in f i gu r e 15 . down sink vdac sr i c = (5) 2 15 10 2 . 3 5 . 0 vdac vdac c r ? ? + = (6) vdac source up c i sr = (7) page 1 5 of 35 1 /31/05
ir3087pbf ov er current setting res i stor r o c set the inductor dc resi stance is utilized t o sense the i nductor current. the copper wi re of inductor has a constant temperature coeffici ent of 3850 p p m/ c , and therefo r e the maximu m indu ctor d cr can b e ca lculate d from equation (8), wh ere r l_max and r l_room are the in du ctor dcr at maxi mum temp erature t l_max and ro om te mperatu r e t_ room res p ec tively. )] ( 10 * 3850 1 [ _ 6 _ _ room max l room l max l t t r r ? ? + ? = ? (8) the cu rre nt sen s e amplifi e r g a in of i r 30 87 d e cre a se s with te mperature at the rate of 1470 ppm/ c, which comp en sate s part of the inducto r dcr i n crea se. the phase ic di e temperatu r e is only a cou p le of degre e s cel s iu s highe r than th e pcb tempe r ature due to the low therm a l impeda nce of mlpq packag e . the mi nimum curren t sense amplifier g a in at the maximum pha se ic temperature t ic_max is ca lculate d from equation (9). )] ( 10 * 1470 1 [ _ 6 _ _ room max ic room cs min cs t t g g ? ? ? ? = ? (9) the total in p u t offset voltage (v cs_tofst ) of curre n t sen s e am plifier in pha se ics i s th e su m of in put offset (v cs_ofs t) o f the amplifier itself and th at cr eate d by the amplifier input bias currents flo w in g throug h the current sen s e r e si st o r s r cs+ and r cs- . ? ? + + ? ? ? + = cs csin cs csin ofst cs tofst cs r i r i v v _ _ (10) the over cu rrent limit is se t by the external re si stor r o c set as defined in equ a tion (1 1), wh ere i limit is the requi re d over current l i mit. i o c set, the bia s curre n t of ocset pin, cha nge s with switchi n g frequ en cy setting resi st or r os c and is d e termined by the curve in fi g u re 1 4 . k p is the ratio of indu ctor p eak cu rrent ove r averag e cu rrent in eac h pha se an d is cal c ulate d fro m equation (12). ocset min cs tofst cs p max l limit ocset i g v k r n i r / ] ) 1 ( [ _ _ _ ? + + ? ? = (11) n i f v l v v v k o sw i o o i p / ) 2 /( ) ( ? ? ? ? ? = (12) no load output voltag e setting resi stor r fb and adap tiv e voltage positio n ing resis t o r r drp a resi stor bet wee n fb pin and the conv erter out put i s u s ed to cre a te output vol t age offset v o_nl ofs t , which i s the differen c e b e t ween v dac voltage an d output voltag e at no lo ad con d it ion. a daptive volta ge po sitioni n g further lowe rs the co nverter voltag e by r o *i o, w here r o is the r e qu ir ed out put impeda nce of the conv erter. r fb is not on ly determine d by i fb , the current flowin g out of fb pin as sho w n in figure 14, bu t also affecte d by the adaptive volt age positio ni ng resi sto r r drp and total input off s et voltage of c u rr e n t s e ns e amp lifie rs . r fb and r drp are dete r min ed by (13 ) an d (14 ) re spe c tively. max l fb o tofst cs nlofst o max l fb r i r n v v r r _ _ _ _ ? ? ? ? ? = (13) o min cs max l fb drp r n g r r r ? ? ? = _ _ (14) body braking tm rela ted resis t ors r bbfb and r bb drp the bo dy brakin g tm durin g dynami c vid can b e di sabl ed by co nne cting bbfb pin to ground. if the feature i s enabl ed, re sistors r bbfb and r bbdrp are nee ded to resto r e t he feed ba ck voltage of the erro r am plifier afte r dynami c vid step do wn. usually r bbfb and r bbdrp are cho s en to match r fb a nd r drp res p ec tively . page 1 6 of 35 1 /31/05
ir3087pbf ir3087 external comp onents pwm ram p resis t or r pw mr mp and capa citor c p w mr mp pwm ram p is generated b y conne cting the resi stor r pwmrmp betwee n a volta ge sou r ce an d pwmrmp pin as well as th e cap a ci tor c pwmrmp between pwm r mp a n d lg nd. ch o o se the de sired p w m ram p mag n itude v pwmrmp and th e cap a citor c pwm r mp in the range of 1 0 0 p f an d 4 70p f, and t hen cal c ulate the re sisto r r p w mrmp from equation (15 ) . to achi eve feed-fo rward voltage mod e control, the resi sto r r pw mrmp should be co nne cte d to the input of the converte r. )] ln( ) [ln( * * * pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? = (15) inductor cur r ent sen s ing capaci tor c cs+ and resi stors r cs+ a nd r cs- the dc re sistance of the i ndu ctor i s util ized to se nse the indu cto r curre n t. usua lly the re sisto r r cs+ and capa citor c cs+ in pa ral l el with the in ducto r are ch ose n to match the time co nstant of the indu ct or, and therefore the voltage across the capa citor c cs+ represents the inducto r curre n t. if the two time consta nts are not the same , the ac comp one nt o f the capa cito r voltage i s d i fferent from t hat of the re al indu ctor cu rre nt. the tim e co nsta nt mismat ch doe s not affect the ave r a g e current sha r ing amon g th e multip le ph ase s , b u t affect the cu rre nt sign al ishare as wel l as the outp u t voltage duri n g the load current tran sie n t if adaptive voltage po sitioni ng is ad opted . measure the indu ctan ce l and the indu ctor dc re sist ance r l . pre-sele ct the ca pacito r c cs+ and calculate r cs+ as follows . + + = cs l cs c r l r (16) the bia s current flowing o u t of the non -inverting in pu t of the curre n t sen s e a m p lifier create s a voltage d r o p acro ss r cs+, which i s eq uivalent t o an in put offset voltage of the cu rr ent sense amplifie r. the off s et affects the accuracy of conve r ter cu rrent si gnal i s hare a s well a s the accura cy of the co nverte r output voltage if adaptiv e voltage positio ning i s adopte d . to redu ce t he offset voltage, a re sisto r r cs- sh ould be ad ded b e twe en the amplifie r i n verting input and the conve r ter o u tput . the res i stor r cs- is de termine d by the ratio of the bias curre n t from the non -invertin g input and the bias curre n t from the inverti ng input. + ? + ? ? = cs csin csin cs r i i r (17) if r cs- is not use d , r cs+ should be cho s en so that th e offset volta ge i s small e noug h. usu a l l y r cs+ sho u l d be le ss than 2 k ? an d therefo r e a large r c cs+ v a lue is n eed e d . ov er temperatur e settin g resis t ors r ho tset1 and r ho tset2 the th re shol d voltage of vrho t com parato r i s pro portion al to t he di e temp e r ature t j (o c) of ph ase ic. dete rmin e the relatio n sh ip between th e die tem perature of pha se ic an d the temperature of the po we r conve r ter accordin g to the po wer l o ss, p c b layo ut and ai rflo w etc, a nd th en ca lculate hotset th resh old voltag e co rrespon d i ng to the allowed maxi mum tempe r ature fro m equation (1 8). 46 . 1 * 10 * 73 . 4 3 + = ? j hotset t v (18) there a r e t w o ways to set the ove r tem peratu r e thre shol d, central setting and l o cal setting. in the cent ral setting, only one re si stor divide r is use d , and the setting vo ltage is co nn ected to ho tset pins of all the phase ics. to redu ce the inf l uen ce of noi se on the a c cura cy of over te mperatu r e setting, a 0.1 u f cap a cito r sho u ld be pla c ed n e xt to hotset p i n of ea ch ph ase i c . in the local setting, a re sisto r div i der p e r pha se is n eede d, and the settin g voltage is con n e c ted to ho tset pin of ea ch p hase. the 0. 1uf d e coupli ng cap a cito r i s n o t ne ce ssary. use vbias as th e referen c e voltage. if r hots et1 is pre-sel e cted, r ho tset2 can be ca lculate d as fol l ows. hotset bias hotset hotset hotset v v v r r ? ? = 1 2 (19) page 1 7 of 35 1 /31/05
ir3087pbf phase dela y timing resistors r phase1 and r phase2 the ph ase d e lay of the i n terleave d m u ltipha se con v erte r i s pro g ramm ed by the re sisto r divider con necte d at rmpin+ o r rmpin- dep endin g on wh ich slop e of the o scill ator ramp is u s ed for the p h a s e delay p r og ra mming of pha se ic, as sho w n in fig u re 3. if the up slop e is u s ed, rmpin+ pin of the p h a s e i c sho u ld be con n e c ted to rmpo ut pi n of the cont rol ic an d rmpin- pin sho u ld b e co nne cted to t he resi stor d i vi der. when rmpo ut v o ltage i s ab o v e the trip v o ltage at rmpin- pin, the pwm latch is set. gat e l beco m e s lo w, and gat e h become s high after the non-overl ap time. if d o w n s l o p e is us ed , rmpin - p i n o f th e p h a s e ic s h ou ld b e c o nn ec te d to r m pou t p i n o f the c o n t r o l ic and rmpin+ pi n sho u ld be co nne cted to t he re sisto r d i vider. whe n rmp o ut v o ltage i s bel ow th e tri p v o ltage at rmpin- pin, the pwm latch is set. gat e l beco m e s lo w, and gat e h become s high after the non-overl ap time. use vbias voltage a s the refere nce for t he re sisto r divider sin c e the oscillato r ramp m agn itude from co ntrol ic tracks vbias voltage. try to avoid both edge s of the oscilla tor ra mp for bette r noise immuni ty. determine the rati o of the progra mming resi st ors correspon di ng to the de sire d switchin g frequ en cie s and p h a s e n u mbe r s. if the re sisto r r phasex 1 is pre- sel e ct e d , t he re sist o r r phasex 2 is determine d as: phasex phasex phasex phasex ra r ra r ? ? = 1 1 2 (20) combined o v er tempera t ure an d pha se delay setting re sistor s r phase1 , r phase2 and r phase3 the over te mperature se tting re si stor divider can b e combi ned with the p h a s e delay re si stor divide r t o save one resi sto r per p hase. cal c ulate th e hotset th reshold volta ge v ho tset co rre sp ondi ng to the all o we d maxim u m tempe r at ure from equation (1 8). if the o v er temperature setting volt age is lowe r than the pha se d e lay setting voltage, vbias*ra phasex , conne ct rmpin+ or rmpin- pin betwe en r p h asex 1 and r phasex 2, an d conn ect hotset pin betwe en r phasex 2 and r p h asex 3. pre-selec t r phase x 1 , ) 1 ( * ) ( 1 2 phasex bias phasex hotset bias phasex phasex ra v r v v ra r ? ? ? ? = (21) ) 1 ( * 1 3 phasex bias phasex hotset phasex ra v r v r ? ? = (22) if the over te mperature se tting voltage i s hi ghe r tha n the ph ase d e lay setting voltage, vbias*ra phasex , co nne ct hotset pin betwe en r ph asex 1 and r p h asex 2. and conne ct rmpi n+ o r rmpi n- between r p h asex 2 and r phasex 3 . p r e- sele ct r p h asex 1 , hotset bias phasex bias phasex hotset phasex v v r v ra v r ? ? ? ? = 1 2 ) ( (23) hotset bias phasex bias phasex phasex v v r v ra r ? ? = 1 3 * (24) boo t str a p capacitor c bst dep endin g o n the duty cy cle an d gate drive current of the pha se ic, a 0.1uf t o 1uf cap a ci tor is n eed ed for the bootstrap ci rcuit. deco upling capa citor s for phase ic 0.1uf-1uf de cou p ling cap a citors a r e re quire d at vcc and vccl pins of ph ase ics. page 1 8 of 35 1 /31/05
ir3087pbf opti-ph ase resis t ors r op 1 and r op 2 a resi sto r divi der i s u s e d to pro g ra m op tiphs pin vol t age, whi c h repre s e n ts th e load cu rrent thre shol d b e lo w which the phase is shut do wn to redu ce the switchi ng loss. pre-sele ct r op 1 , and cal c ulate r op 2 accordi ng to equation ( 2 5) , w h er e i o_ op is the opti-pha se she dding curre n t threshold. cs tofst cs l op o bias cs tofst cs l op o op op g v r n i v g v r n i r r ? + ? ? + ? ? = ] ) / [( * ] ) / [( _ _ _ _ 1 2 (25) the co nne cti on of optiphs pin to vbias pin disabl es this fun c tio n and keep s the pha se al ways on. voltage loop comp ensation the adaptive voltage posi tioning (avp) is usually adopted in the computer applications to i m prove the transient respon se and redu ce th e p o we r lo ss at heavy load. l i ke cu rre n t mode control, the ad aptive voltage p o sitio n ing loo p introdu ce s extra zero to th e voltage l o o p and splits t he do uble po les of th e p o w er sta ge, which ma ke th e voltage loop compe n s ation mu ch easi e r. re sist o r s r fb and r drp a r e cho s e n a c cording to eq uation s (13 ) and (14 ) , a n d the sele ction of comp en sa tion types depe nd s on the output ca pacito r s u s e d in the converter. fo r the applicatio ns using elect r olytic, polymer or al- polymer cap a citors a nd runnin g at lower freq uen cy, type ii compensation sho w n in fig u re 8(a ) is u s u a ll y enough . while for the appli c ations using cerami c capacitors and running at higher fre quency, type iii compensation shown i n figure 8(b ) is preferred. for a ppli c atio ns whe r e av p is not requi red, the com pen sati on i s t he same a s f o r the reg u lar voltage mod e co ntrol. for co nverte r usi n g polymer, al -polym er, a nd ce ra mic ca pa citors, which hav e mu ch hig h e r es r ze ro freque ncy, type iii comp ensation is re quire d as sho w n in figu re 8(b ) with r dr p and c drp removed. rc p cc p 1 eaou t cc p rf b rd rp vo+ v drp vd ac + - eaou t fbfb cfb cdrp rcp eao u t ccp 1 cc p rfb rd rp vo+ v drp vd ac fb + - eaou t rfb 1 (a) t y pe ii com pens atio n (b) t y pe iii compens ation figure 8. voltage loop co mpen sation n e twork page 1 9 of 35 1 /31/05
ir3087pbf t y pe ii compensa tion fo r avp applic ations determine th e com pen sati on at no loa d , the wo rst ca se condi tio n . cho o se the crossove r fre q uen cy fc bet wee n 1/10 and 1/5 of th e swit chin g freque ncy pe r pha se. assu me the time con s tant of the re si stor a nd ca pa citor across the output in du ctors mat c he s t hat of the ind u ctor, and de termine r cp and c cp fro m equatio ns (26 ) a nd (27 ) , whe r e l e and c e are t he e quivalen t indu ctan ce of output i n d u ctors and t he e quivalen t cap a cita nce of outp u t ca pacito r s r e spec tively. 2 2 ) * * * 2 ( 1 * ) 2 ( c c o pwmrmp fb e e c cp r c f v v r c l f r + ? ? ? ? ? = (26) cp e e cp r c l c ? ? = 10 (27) c cp1 is optio nal and may be nee ded in some a ppli c a t ions to red u ce the jitter ca use d by the high frequ en cy noise. a cerami c ca pa citor bet wee n 10pf and 2 2 0pf is u s ually enoug h. t y pe iii com p ensation for avp applications determine th e com pen sati on at no lo a d , the wo rst ca se con d ition. assu me th e time co ns t ant of the re sisto r an d cap a cito r a c ross the outpu t inducto rs m a tche s th at of the ind u cto r , the cro s sover frequ en cy an d pha se ma rg in of th e voltage loop can b e estim a ted by equa tions (2 8) a n d (29), where r le is the eq uivalent re sist ance of indu ctor dcr. . le fb cs e drp c r r g c r f ? ? = * * 2 1 (28) 180 ) 5 . 0 tan( 90 1 ? ? = a c (29) cho o se the d e sired cro s so ver frequ en cy fc aro und fc1 es timate d b y equation (2 8) o r ch oo se fc between 1/ 10 an d 1/5 of the swi t ching freq ue ncy p e r pha se, and sele ct the comp o n e n ts to en sure the sl ope of close loop gai n is -2 0db /dec aro und the crossove r freque ncy. cho o se re si stor r fb1 a c cordin g to eq uation (30 ) , and d e termi n e c fb an d r drp from equation s (3 1) and (3 2). fb fb r r 2 1 1 = to fb fb r r 3 2 1 = (30) 1 4 1 fb c fb r f c ? ? = (31) drp fb fb fb drp r c r r c ? + = ) ( 1 (32) r cp an d c cp have limite d effect on the cro s sove r fre quen cy, and are used only to fine tun e t he cro s sove r freque ncy and tran sie n t load re sp on se. determi ne r cp and c cp from equatio ns (3 3) a nd (34). o pwmrmp fb e e c cp v v r c l f r ? ? ? ? ? = 2 ) 2 ( (33) cp e e cp r c l c ? ? = 10 (34) c cp1 is optio nal and may be nee ded in some a ppli c a t ions to red u ce the jitter ca use d by the high frequ en cy noise. a cerami c ca pa citor bet wee n 10pf and 2 2 0pf is u s ually enoug h. page 2 0 of 35 1 /31/05
ir3087pbf t y pe iii com p ensation for non-avp applications re sist o r r fb is cho s en a c cordin g to eq u a tions (1 3), a nd resi stor r drp and capa citor c drp a r e not n eed ed. cho o se the cro s sover frequ en cy fc betwe en 1/1 0 and 1/5 of th e sw itching f r eque ncy p e r pha se and se lect the de sired p h a s e margi n c. calcul ate k factor from equa tion (35 ) , and determi n e the com pone nt values b a sed on equation s (3 6) t o (40 ) , )] 5 . 1 180 ( 4 tan[ c k t s (35) k v v f c l r r o pwmrmp c e e fb cp 2 ) 2 ( s (36) cp c cp r f k c s 2 (37) cp c cp r k f c s 2 1 1 (38) fb c fb r f k c s 2 (39) fb c fb c k f r s 2 1 1 (40) current s h are loop compens a tion the crossove r fre que ncy of the cu rrent s hare loo p sh o u ld b e at lea s t one de cad e lowe r th an th at of the volta ge lo op in orde r to eli m inate the in teractio n b e twee n the two loop s. a ca p a citor fro m s c omp to g r o und i s usuall y enou gh for the sha r e loop com p ensation. ch oose the cro s sover freq u ency of current sha r e lo op (f ci ) based on the cro s sove r fre quen cy of voltage loop (f c), and dete r min e the c sco m p , 6 _ 10 * 05 . 1 * 2 * )] ( * * * 2 1 [ * * * * * * 65 . 0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c s s (41) whe r e f mi is the pwm gai n in the curre n t share loop , ) ( * ) ( * * * dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f ( 42) page 2 1 of 35 1 /31/05
ir3087pbf design e x ample 1 - vrm 10 2u conve r ter specifications input voltage : v i =12 v dac voltag e: v dac =1.35 v no lo ad out put voltage o ffset: v o_nlof st =20 mv output current: i o =105 a dc maximum output current: i oma x =120 a dc output imped ance: r o =0. 9 1 m ? vcc ready to vcc po wer good delay: t vccpg =0- 1 0 m s soft start tim e : t ss =2 ms over current delay: t ocde l< 0.5ms dynami c vid do wn-sl ope slew rate: s r down = 2 .5mv/us over tem perature th re sh old: t pcb =11 5 oc power stage phase num b er: n=6 switchin g fre quen cy: f sw =400 khz output indu ctors: l = 22 0 n h , r l =0.47 m ? output ca pa citors: al-pol ymer, c=560 uf, r c = 7m ? , numbe r cn =10 ir308 1a ex tern al co mpone n ts oscillator resistor ros c once the switching frequ ency i s cho s en, r os c ca n be d e termi ned fro m the cu rve in fig u re 1 3 . fo r swit chin g freque ncy of 400 khz pe r p hase, cho o se r os c =30.1k ? soft sta r t c a pacitor c ss/ del determine the s o ft s t art capac itor fr om t he req u ired soft start time. uf v t i c o ss chg del ss 1 . 0 10 * 20 35 . 1 10 * 2 10 * 70 3 3 6 / the s o ft s t art delay time is ms i c t chg del ss ssdel 86 . 1 10 * 70 3 . 1 10 * 1 . 0 3 . 1 6 6 / the po we r go od delay time is ms i v c t chg o del ss vccpg 58 . 1 10 * 70 ) 3 . 1 33 . 1 735 . 3 ( * 10 * 1 . 0 ) 3 . 1 735 . 3 ( * 6 6 / over current delay time is ms i c t ocdischg del ss ocdel 29 . 0 10 * 40 115 . 0 * 10 * 1 . 0 115 . 0 * 6 6 / vdac sle w rate progra mming capa citor c vdac and re sisto r r vdac from fig u re 15, the sin k curre n t of vdac pin corresp ondi ng to 400khz (r os c =30.1 k ? ) i s 76ua. cal c ulate the vdac do wn -slop e sle w -ra t e prog rammi ng ca pa citor from the requi red do wn -slo pe sle w rate. page 2 2 of 35 1/ 3 1 / 0 5
ir3087pbf nf sr i c down sink vdac 4 . 30 10 / 10 * 5 . 2 10 * 76 6 3 6 = = = ? ? ? , choo se c vd ac =33n f cal c ulate the prog ram m ing resi stor. ? = + = + = ? ? ? 5 . 3 ) 10 * 33 ( 10 * 2 . 3 5 . 0 10 * 2 . 3 5 . 0 2 9 15 2 15 vdac vdac c r from fig u re 15, the sou r ce curre n t of vdac pin i s 11 0ua. the vdac up-slo pe sle w rate is us mv c i sr vdac source up / 3 . 3 10 * 33 10 * 110 9 6 = = = ? ? ov er current setting res i stor r o c set the room te mperature is 25oc an d the target p c b t e mpe r at ure i s 1 00 o c . th e pha se ic di e tempe r atu r e is abo ut 1 oc high er tha n that of phase ic, and the indu ct or temp eratu r e is clo s e to pcb temperature. cal c ulate ind u ctor dc re si stan ce at 100 oc, ? = ? ? + ? = ? ? + ? = ? ? ? m t t r r room max l room l max l 61 . 0 )] 25 100 ( 10 * 3850 1 [ 10 * 47 . 0 )] ( 10 * 3850 1 [ 6 3 _ 6 _ _ the cu rrent sense amplifie r gain is 3 4 at 25oc, and its gain at 101o c is calculate d as, 2 . 30 )] 25 101 ( 10 * 1470 1 [ 34 )] ( 10 * 1470 1 [ 6 _ 6 _ _ = ? ? ? ? = ? ? ? ? = ? ? room max ic room cs min cs t t g g set the over current limit at 135a. from fi gu re 1 4 , the bias curre n t of ocset pin (i o c set ) is 41ua with r os c =30.1 k ? . the total current sen s e amplifier inp u t offset volt ag e is 0.55 mv, whi c h i n cl ude s the offset created by the curre n t se nse am plifier input re sisto r mismat ch. cal c ulate con s tant k p, the ratio of induct o r pea k curre n t ov er avera ge cu rrent in each pha se, 3 . 0 6 / 135 ) 2 10 * 400 12 10 * 220 /( 33 . 1 ) 33 . 1 12 ( / ) 2 /( ) ( 3 9 = ? ? ? ? ? = ? ? ? ? ? = ? n i f v l v v v k limit sw i o o i p ocset min cs tofst cs p max l limit ocset i g v k r n i r / ] ) 1 ( [ _ _ _ ? + + ? ? = ? = ? + ? ? = ? ? ? k 3 . 13 ) 10 * 41 /( 2 . 30 ) 10 * 55 . 0 3 . 1 10 * 61 . 0 6 135 ( 6 3 3 no load output voltag e setting resi stor r fb and adap tiv e voltage positio n ing resis t o r r drp from fig u re 14, the bias current of fb pin is 41ua wit h r os c =30.1 k ? . ? = ? ? ? ? ? = ? ? ? ? ? = ? ? ? ? ? ? 365 10 * 61 . 0 10 * 41 10 * 91 . 0 6 10 * 55 . 0 10 * 20 10 * 61 . 0 3 6 3 3 3 3 _ _ _ _ max l fb o tofst cs nlofst o max l fb r i r n v v r r ? = ? ? ? = ? ? ? = ? ? k r n g r r r o min cs max l fb drp 21 . 1 10 * 91 . 0 6 2 . 30 10 * 61 . 0 365 3 3 _ _ bod y braking related re sistors r bbfb and r bbdr p n/a. the bod y brakin g du ri ng dynami c vid is disa ble d . page 2 3 of 35 1/ 3 1 / 0 5
ir3087pbf ir3087 external comp onents pwm ram p resis t or r pw mr mp and capa citor c p w mr mp set pwm ramp magnitude v pwmrmp =0.8v. choo se 220 pf for pwm ramp capa citor c pw mrmp , and calcul ate the resi st o r r pw mrmp , )] ln( ) [ln( pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? ? ? ? = ? = ? ? ? ? ? ? ? = ? k 1 . 16 )] 8 . 0 35 . 1 12 ln( ) 35 . 1 12 [ln( 10 * 220 10 * 400 12 33 . 1 12 3 , choo se r p w mrmp =16.2 k ? inductor cur r ent sen s ing capaci tor c cs+ and resi stors r cs+ a nd r cs- cho o s e c cs+ =47 n f, and calcul ate r cs+, ? = = = ? ? ? + + k c r l r cs l cs 0 . 10 10 * 47 ) 10 * 47 . 0 /( 10 * 220 9 3 9 the bia s cu rrents of csin+ and cs in- are 0.25 ua a nd 0.4ua re spec tively. cal c ulate resi sto r r cs- , ? = ? = ? = + ? k r r cs cs 2 . 6 10 * 0 . 10 4 . 0 25 . 0 4 . 0 25 . 0 3 , choo se r cs- =6. 1 9 k ? ov er temperatur e settin g resis t ors r ho tset1 and r ho tset2 use ce ntral o v er-temp e rature setting a nd set the te mperatur e th resh old at 11 5 oc, whi c h co rre sp ond s to the ic die temperature of 116 oc. ca lculate the hotset thre shold voltage corre s p ondin g to the temperatu r e thre shold s . v t v j hotset 79 . 1 241 . 1 116 10 * 73 . 4 241 . 1 * 10 * 73 . 4 3 3 = + ? = + = ? ? p r e- sele ct r h o tset1 =10.0 k ? , ? = ? ? = ? ? = k v v v r r hotset bias hotset hotset hotset 57 . 3 79 . 1 8 . 6 79 . 1 10 * 10 3 1 2 phase dela y timing resistors r phase1 and r phase2 use ce ntral o v er-temp e rature setting a nd set the te mperatur e th resh old at 11 5 oc, whi c h co rre sp ond s to the ic die temperature of 116 oc. ca lculate the hotset thre shold voltage corre s p ondin g to the temperatu r e thre shold s . the p h a s e d e lay re si stor ratio s fo r p hases 1 to 6 at 4 0 0 k hz of switching frequ en cie s are ra phas e1 = 0 .628, ra phase2 =0. 415, ra phas e3 = 0 .202, ra phase4 = 0 .246, ra phase5 =0.44 1 an d ra phase5 =0.6 37 sta r ting f r om do wn- slop e. pre-sel e ct r phase11 =r phase21 =r phase31 =r phase41 =r ph ase51 = r pha se61 =10 k ? , ? = ? ? = ? ? = k r ra ra r phase phase phase phase 9 . 16 10 * 10 628 . 0 1 628 . 0 1 3 11 1 1 12 r phase22 =7. 15k , r phas e32 =2. 5 5 k , r phase42 =3. 24k , p phase52 =7. 8 7 k , r phase62 = 17.4 k boo t str a p capacitor c bst cho o s e c bst =0. 1 u f deco upling capa citor s for phase ic and po w e r s t age cho o s e c vcc = 0 .1uf, c vccl =0.1uf page 2 4 of 35 1/ 3 1 / 0 5
ir3087pbf opti-ph ase resis t ors r op 1 and r op 2 disable opti-pha se fu nctio n for pha se 1 to kee p it r unni ng at a n y load cond ition. set the opti-ph a se she ddin g curre n t threshold for ph ases 2 to 5 at 20 a. pre-sel e ct r op21 = 10.0 k ? , and cal c ulate r op 22 . : 438 34 * ] 10 * 55 . 0 10 * 47 . 0 * ) 6 / 20 [( 8 . 6 34 * ] 10 * 55 . 0 10 * 47 . 0 * ) 6 / 20 [( * 10 * 20 ] ) / [( * ] ) / [( 3 3 3 3 3 _ _ _ _ 21 22 cs tofst cs l op o bias cs tofst cs l op o op op g v r n i v g v r n i r r cho o s e r op22 = 442 ? r op31 = r op 41 = r op51 = r op61 = 10.0 k ? r op32 = r op42 = r op52 = r op62 = 442 ? voltage loop comp ensation type ii comp ensation i s u s ed fo r the co nverter with al-pol ymer o u tput ca pa citors. cho o se the cro s sover freque ncy fc=4 0khz, wh ich is 1/1 0 of the swit chin g freque ncy pe r phase, and d e termin e rcp and c cp . : k r c f v v r c l f r c c o ramp fb e e c cp 0 . 2 ) 10 * 7 * 10 * 560 * 10 * 40 * 2 ( 1 * ) 10 20 35 . 1 ( 8 . 0 365 ) 10 10 560 ( ) 6 / 10 220 ( ) 10 40 2 ( ) * * * 2 ( 1 * ) 2 ( 2 3 6 3 3 6 9 2 3 2 2 s s s s nf r c l c cp e e cp 71 10 0 . 2 ) 10 * 10 560 ( ) 6 / 10 220 ( 10 10 3 6 9 , choo se c cp =68 n f cho o s e c cp1 =47 p f to red u ce hi gh freq uen cy noise. current s h are loop compens a tion the cro s sove r frequ en cy of the current sha r e loo p f ci shoul d be at least one d e c ad e lower th an that of the voltage loop f c . choo se the cro s so ver frequ en cy of current sh are loo p f ci =4 kh z , a nd calculate c sco m p , 011 . 0 ) 35 . 1 12 ( * ) 35 . 1 8 . 0 12 ( 8 . 0 * 10 * 400 * 10 * 220 * 10 * 2 . 16 ) ( * ) ( * * * 3 12 3 dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f 6 _ 10 * 05 . 1 * 2 * )] ( * * * 2 1 [ * * * * * * 65 . 0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c s s 6 3 4 4 6 3 3 3 10 * 05 . 1 * 10 * 4 2 ) 10 * 1 . 9 * 105 33 . 1 ( 011 . 0 * ] 105 ) 10 * 1 . 9 * 105 33 . 1 ( * 10 * 10 * 560 * 10 * 4 * 2 1 [ * ) 6 10 * 47 . 0 ( * 34 * 105 * 12 * 10 * 2 . 16 * 65 . 0 s s nf 4 . 31 cho o s e c sc o m p =33nf. page 2 5 of 35 1/ 3 1 / 0 5
ir3087pbf design example 2 - evrd 10 high frequency all-ce ramic converte r specifications input voltage : v i =12 v dac voltag e: v dac = 1 .3 v no lo ad out put voltage o ffset: v o_nlof st =20 mv output current: i o =105 a dc maximum output current: i oma x =120 a dc output imped ance: r o =0. 9 1 m ? vcc ready to vcc po wer good delay: t vccpg =0- 1 0 m s soft start tim e : t ss =3ms over current delay: t ocde l <0. 5 ms dynami c vid do wn-sl ope slew rate: s r down = 2 .5mv/us over tem perature th re sh old: t pcb =11 5 oc power stage phase num b er: n=6 switchin g fre quen cy: f sw =800 khz output indu ctors: l = 10 0 n h , r l =0.5 m ? output ca pa citors: ce ram i c, c=22uf, r c = 2m ? , nu mber cn =62 ir308 1a ex tern al co mpone n ts oscillator resistor ros c once the swi t ching f r equ e n cy is ch ose n , r os c can be dete r min ed from th e curve in fig u r e 1 3 data sheet. for swit chin g freq uen cy of 800 khz pe r pha se, choo se r os c =13.3 k ? soft sta r t c a pacitor c ss/ del determine the s o ft s t art capac itor fr om t he req u ired soft start time. uf v t i c o ss chg del ss 16 . 0 10 * 20 3 . 1 10 * 3 10 * 70 3 3 6 / , choo se c ss/ del =0.15uf the s o ft s t art delay time is ms i c t chg del ss ssdel 8 . 2 10 * 70 3 . 1 10 * 15 . 0 3 . 1 6 6 / the po we r go od delay time is ms i v c t chg o del ss vccpg 4 . 2 10 * 70 ) 3 . 1 33 . 1 735 . 3 ( * 10 * 15 . 0 ) 3 . 1 735 . 3 ( * 6 6 / over current delay time is ms i c t ocdischg del ss ocdel 43 . 0 10 * 40 115 . 0 * 10 * 15 . 0 115 . 0 * 6 6 / vdac sle w rate progra mming capa citor c vdac and re sisto r r vdac from fig u re 15, the sin k current of vdac pin corre s p ondin g to 800 khz (r os c =1 3.3k ? ) i s 170 ua. calcul ate the vdac do wn -slop e sle w -ra t e prog rammi ng ca pa citor from the requi red do wn -slo pe sle w rate. page 2 6 of 35 1/ 3 1 / 0 5
ir3087pbf nf sr i c down sink vdac 68 10 / 10 * 5 . 2 10 * 170 6 3 6 = = = ? ? ? cal c ulate the prog ram m ing resi stor. ? = + = + = ? ? ? 2 . 1 ) 10 * 68 ( 10 * 2 . 3 5 . 0 10 * 2 . 3 5 . 0 2 9 15 2 15 vdac vdac c r from fig u re 15, the sou r ce curre n t of vdac pin i s 25 0ua. the vdac up-slo pe sle w rate is us mv c i sr vdac source up / 7 . 3 10 * 68 10 * 250 9 6 = = = ? ? ov er current setting res i stor r o c set the room te mperature is 25oc an d the target p c b t e mpe r at ure i s 1 00 o c . th e pha se ic di e tempe r atu r e is abo ut 1 oc high er tha n that of phase ic, and the indu ct or temp eratu r e is clo s e to pcb temperature. cal c ulate ind u ctor dc re si stan ce at 100 oc, ? = ? ? + ? = ? ? + ? = ? ? ? m t t r r room max l room l max l 64 . 0 )] 25 100 ( 10 * 3850 1 [ 10 * 5 . 0 )] ( 10 * 3850 1 [ 6 3 _ 6 _ _ the cu rrent sense amplifie r gain is 3 4 at 25oc, and its gain at 101o c is calculate d as, 2 . 30 )] 25 101 ( 10 * 1470 1 [ 34 )] ( 10 * 1470 1 [ 6 _ 6 _ _ = ? ? ? ? = ? ? ? ? = ? ? room max ic room cs min cs t t g g set the over current limit at 135a. from fi gu re 1 4 , the bias curre n t of ocset pin (i o c set ) is 90ua with r os c =13.3 k . the total current sen s e amplifier inp u t offset volt ag e is 0.55 mv, whi c h i n cl ude s the offset created by the curre n t se nse am plifier input re sisto r mismat ch. cal c ulate con s tant k p, the ratio of induct o r pea k curre n t ov er avera ge cu rrent in each pha se, 32 . 0 6 / 135 ) 2 10 * 800 12 10 * 100 /( 28 . 1 ) 28 . 1 12 ( / ) 2 /( ) ( 3 9 = ? ? ? ? ? = ? ? ? ? ? = ? n i f v l v v v k limit sw i o o i p ocset min cs tofst cs p max l limit ocset i g v k r n r r / ] ) 1 ( [ _ _ _ ? + + ? ? = ? = + ? ? = ? ? ? k 34 . 6 ) 10 * 90 /( 2 . 30 * ) 10 * 55 . 0 32 . 1 10 * 64 . 0 6 135 ( 6 3 3 no load output voltag e setting resi stor r fb and adap tiv e voltage positio n ing resis t o r r drp from fig u re 14, the bias current of fb pin is 90ua wit h r os c =13.3 k . ? = ? ? ? ? = ? ? ? ? ? = ? ? ? ? ? ? 162 10 * 64 . 0 * 10 * 90 10 * 91 . 0 6 10 * 55 . 0 10 * 20 10 * 64 . 0 3 6 3 3 3 3 _ _ _ _ max l fb o tofst cs nlofst o max l fb r i r n v v r r ? = ? ? = ? ? ? = ? ? 576 10 * 91 . 0 6 2 . 30 * 10 * 64 . 0 162 3 3 _ _ o min cs max l fb drp r n g r r r bod y braking related re sistors r bbfb and r bbdr p n/a. the bod y brakin g du ri ng dynami c vid is disa ble d . page 2 7 of 35 1/ 3 1 / 0 5
ir3087pbf ir3087 external comp onents pwm ram p resis t or r pw mr mp and capa citor c p w mr mp set pwm ra mp magnitu d e v pwmrmp =0.75v. choo se 100pf fo r pwm ram p capa citor c p w mrmp , and ca lculate the resi st o r r pw mrmp , )] ln( ) [ln( * * * pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? = = ? = ? ? ? ? ? ? ? ? k 2 . 18 )] 75 . 0 3 . 1 12 ln( ) 3 . 1 12 [ln( 12 10 * 100 3 10 * 800 12 28 . 1 inductor cur r ent sen s ing capaci tor c cs+ and resi stors r cs+ a nd r cs- cho o se 47nf for cap a cito r c cs+, and cal c ulate r cs+, ? = = = ? ? ? + + k c r l r cs l cs 22 . 4 10 * 47 ) 10 * 5 . 0 /( 10 * 100 9 3 9 the bia s cu rrents of csin+ and cs in- are 0.25 ua a nd 0.4ua re spec tively. cal c ulate resi sto r r cs- , ? = ? = ? = + ? k r r cs cs 61 . 2 10 * 22 . 4 4 . 0 25 . 0 4 . 0 25 . 0 3 combined o v er tempera t ure an d pha se delay setting re sistor s r phasex1 , r phasex2 and r phasex3 the over tem peratu r e setting re sisto r di vider is co mb ined wi th the pha se delay resi stor divide r. set the temperatu r e threshold at 115 o c , whi c h co rrespon d s to the ic di e te mpe r ature of 116 o c , and cal c ulate the hotse t thre shol d voltage co rre s po ndin g to the tempe r atu r e thre sh old s . v t v j hotset 79 . 1 241 . 1 116 10 * 73 . 4 241 . 1 10 * 73 . 4 3 3 = + ? = + ? = ? ? the p h a s e d e lay re si stor ratio s fo r p hases 1 to 6 at 8 0 0 k hz of switching frequ en cie s are ra phas e1 = 0 .665, ra phase2 =0. 432, ra phas e3 = 0 .198, ra phase4 = 0 .206, ra phase5 =0.40 1 an d ra phase5 =0.5 97 sta r ting f r om do wn- slop e. the over te mperature se tting voltage of phases 1, 2, 5, and 6 is lowe r tha n the pha se delay setting voltage, vbias*ra phasex . pre-selec t r phase11 =10 k , ? = ? ? ? ? ? = ? ? ? ? = k ra v r v v ra r phasex bias phasex hotset bias phasex phasex 1 . 12 ) 665 . 0 1 ( 8 . 6 10 * 10 ) 79 . 1 8 . 6 665 . 0 ( ) 1 ( * ) ( 3 1 2 ? = ? ? = ? ? = k ra v r v r phasex bias phasex hotset phasex 87 . 7 ) 665 . 0 1 ( * 8 . 6 10 * 1 . 12 79 . 1 ) 1 ( * 3 1 3 r phase21 = 10k , r phase22 =2. 9 4 k , r p h ase23 =4. 6 4 k r phase51 = 10k , r phase52 =2. 3 2 k , r p h ase53 =4. 4 2 k r phase61 = 10k , r phase62 =8. 2 5 k , r p h ase63 =6. 4 9 k the over tem peratu r e setting voltage of phase s 3 a n d 4 is highe r than the pha se delay setting voltage, vbias*ra phasex . pre-selec t r phasex1 =10 k , ? = ? ? ? ? = ? ? ? ? = 887 79 . 1 8 . 6 10 * 10 ) 8 . 6 198 . 0 79 . 1 ( ) ( 3 31 3 32 hotset bias phase bias phase hotset phase v v r v ra v r ? = ? ? ? = ? ? = k v v r v ra r hotset bias phase bias phase phase 67 . 2 79 . 1 8 . 6 10 * 10 8 . 6 198 . 0 * 3 31 3 33 page 2 8 of 35 1/ 3 1 / 0 5
ir3087pbf r phase41 = 10k ? , r phase42 =76 8 ? , r pha se43 =2. 8 0 k ? boo t str a p capacitor c bst cho o s e c bst =0. 1 u f deco upling capa citor s for phase ic and po w e r s t age cho o s e c vcc = 0 .1uf, c vccl =0.1uf opti-ph ase resis t ors r op 1 and r op 2 disable opti-pha se fu nctio n for pha se 1 to kee p it r unni ng at a n y load cond ition. set the opti-ph a se she ddin g curre n t threshold for ph ases 2 to 5 at 20 a. pre-sel e ct r op21 = 10.0 k ? , and cal c ulate r op 22 . : 464 34 * ] 10 * 55 . 0 10 * 5 . 0 * ) 6 / 20 [( 8 . 6 34 * ] 10 * 55 . 0 10 * 5 . 0 * ) 6 / 20 [( * 10 * 20 ] ) / [( * ] ) / [( 3 3 3 3 3 _ _ _ _ 21 22 cs tofst cs l op o bias cs tofst cs l op o op op g v r n i v g v r n i r r r op31 = r op 41 = r op51 = r op61 = 10.0 k ? r op32 = r op42 = r op52 = r op62 = 464 ? voltage loop comp ensation type iii compensation is used for the converter with only cerami c output capacitors. the crossover frequency and pha se ma rgin of the voltage loop can be estimated a s follows. khz r r g c r f le fb cs e drp c 146 ) 6 / 10 * 5 . 0 ( 162 34 ) 10 * 22 62 ( 2 576 2 3 6 1 s s q 63 180 ) 5 . 0 tan( 90 1 s t a c cho o s e : 110 162 3 2 3 2 1 fb fb r r cho o se the d e sired cro s so ver frequ en cy fc (=1 4 0 k hz) aroun d fc1 e s timated ab o v e, and cal c ul ate nf r f c fb c fb 2 . 5 110 10 * 140 4 1 4 1 3 1 s s , choo se c fb =5. 6 n f nf r c r r c drp fb fb fb drp 7 . 2 576 10 * 6 . 5 ) 110 162 ( ) ( 9 1 : k v v r c l f r o ramp fb e e c cp 65 . 1 10 * 20 3 . 1 75 . 0 * 162 ) 62 10 * 22 ( ) 6 / 10 * 100 ( ) 10 * 140 2 ( ) 2 ( 3 6 9 2 3 2 s s nf r c l c cp e e cp 27 10 65 . 1 ) 62 * 10 * 22 ( ) 6 / 10 * 100 ( 10 10 3 6 9 cho o s e c cp1 =47 p f to red u ce hi gh freq uen cy noise. page 2 9 of 35 1/ 3 1 / 0 5
ir3087pbf current s h are loop compens a tion the cro s sove r frequ en cy of the current sha r e loo p f ci shoul d be at least one d e c ad e lower th an that of the voltage loop f c . choo se the cro s so ver frequ en cy of current sh are loo p f ci =3 . 5 kh z , a nd ca lculate c sco m p , 011 . 0 ) 3 . 1 12 ( * ) 3 . 1 75 . 0 12 ( 75 . 0 * 10 * 800 * 10 * 100 * 10 * 2 . 18 ) ( * ) ( * * * 3 12 3 = ? ? ? = ? ? ? = ? dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f 6 _ 10 * 05 . 1 * 2 * )] ( * * * 2 1 [ * * * * * * 65 . 0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c ? ? + = 6 4 4 6 3 3 10 * 05 . 1 * 3500 2 ) 10 * 1 . 9 * 105 33 . 1 ( 011 . 0 * ] 105 ) 10 * 1 . 9 * 105 33 . 1 ( * 62 * 10 * 22 * 3500 * 2 1 [ * ) 6 10 * 5 . 0 ( * 34 * 105 * 12 * 10 * 2 . 18 * 65 . 0 ? ? ? ? + = ? ? ? ? nf 6 . 20 = page 3 0 of 35 1/ 3 1 / 0 5
ir3087pbf layout guidelines the followi ng layout guidel ines a r e reco mmend ed to redu ce the p a ra sitic ind u ctance a nd re sista n ce of the pcb layout, therefore minimi zin g the noise couple d to the ic. ? dedi cate at least o ne mi d d le laye r for a groun d pla ne, whi c h is t hen split into sign al g r oun d plane (l gnd) an d power g r ou nd plane (pg n d). ? con n e c t pgnd to lg nd pins of each phase ic to t he grou nd ta b, which is tied to lgnd and pgnd pl ane s r e spec tively t h r o ugh vias . ? in orde r to re duce the noi se cou p led to scomp pin of phase ic, use a d edi cat ed wire to co nne ct the cap a citor c sco m p dire ctly to lgnd pin. ho weve r, co nne ct pwm ramp ca pacito r c pwm r mp , phase d e lay pro g ram m ing resi st o r r pha se2 or r phas e3, decou plin g cap a cito r c vcc to lgnd plane throug h vias. ? place curre n t sen s e resi st ors and cap a c itors (r cs+ , r cs- , c cs+ , and c cs- ) close to p h a s e ic. use kelvin con n e c tion fo r the indu ctor current sen s e wire s, but s eparate the two wi re s by grou nd polyg on. the wi re from th e in du c t or te r m ina l to rc s- s h o u l d no t cr os s o v er t he fa st tran sition nod es, i.e. swit chin g nod es, gate drive outputs a nd b ootstra p nod e s . ? place the de couplin g cap a c itors c vcc a nd c vccl a s clo s e as po ssible to vcc a nd v c cl pi n s of the pha se ic r e spec tively. ? ? ? place the p h a se ic as clo s e a s po ssibl e to the mos f et s to re du ce the p a ra sit i c re si stan ce and ind u cta n ce of the gate drive paths. place th e in p u t ce rami c ca pacito r s cl ose to the drain of top m o sf et and the source of bott o m mosfet . use combi nation of different pa ckage s of ce ramic capa cito rs. there a r e t w o switching p o we r lo op s. one l oop in cl ude s the input c a pac i tors , top m o sfet, indu ctor, o u tput cap a cito rs an d the l oad; a nother loo p consi s ts of b o ttom mosfe t , indu ctor , o u tput capa cit o rs an d th e l oad. route th e switching po wer paths usi ng wide and sh o r t trac es or p o lygon s; use multip le vias for conn ectio n s betwe en laye rs. lg n d vcc v ccl ea in sco m p ga t e l ga t e h pg nd csi n + csi n - daci n biasin to s i g n a l b u s i s ha re to i n d u ctor to pg nd plan e to l g nd pl an e c vc c c vc cl to v i n to l g nd pla n e r pw m r mp c pw m r mp c sc o m p r bia s in r cs + d bst vcch c bst to g a te dr iv e vol t age r pha se2 r ph ase1 vrh o t hotse t rm p i n - rm p i n + op tip h s eai n p w mr mp to t o p m o sf et pgnd pl a n e lgn d pl a n e to s w it ching node gro u nd pol y gon c cs + r cs- c cs - g r ound po l y gon to l g nd pla n e t o b o ttom m o sf et lg n d vcc v ccl ea in sco m p ga t e l ga t e h pg nd csi n + csi n - daci n biasin to s i g n a l b u s i s ha re to i n d u ctor to pg nd plan e to l g nd pl an e c vc c c vc cl to v i n to l g nd pla n e r pw m r mp c pw m r mp c sc o m p r bia s in r cs + d bst vcch c bst to g a te dr iv e vol t age r pha se2 r ph ase1 vrh o t hotse t rm p i n - rm p i n + op tip h s eai n p w mr mp to t o p m o sf et pgnd pl a n e lgn d pl a n e to s w it ching node gro u nd pol y gon c cs + r cs- c cs - g r ound po l y gon to l g nd pla n e t o b o ttom m o sf et page 3 1 of 35 1/31/05
ir3087pbf pcb me tal a nd compon e n t placemen t ? lead lan d wi dth shoul d b e equ al to no minal part lea d wi dth. the minimum lea d to l ead spa c ing shoul d b e ? 0.2mm to minimiz e shorting. ? lead l and l e ngth shoul d be eq ual to maximum pa rt lead l ength + 0.2 m m o u tboard exte nsio n + 0.05 mm inboa rd exte nsio n. the outboa rd ext ensi on en su re s a la rge a nd inspe c tabl e toe fillet, and the inbo a r d extension will accommodat e any part mi salignment and ensure a fillet. ? cente r pad l and length a nd width sho u ld be equ al to maximum part pad len g t h and width. however, the minimum met a l to m e tal spaci ng sh oul d be ? 0.17 mm for 2 oz. co ppe r ( ? 0 . 1mm for 1 o z . copp er an d ? 0.23mm for 3 oz. cop per) ? four 0.3m m diamete r vias shall be pla c ed in the pa d land sp ace d at 1.2mm, and co nne cte d to ground t o minimize the noise effect o n the ic, and to transfe r he at to the pcb. page 3 2 of 35 1/31/05
ir3087pbf solder resis t ? the solde r re sist sho u ld b e pulle d awa y from the m e tal lead la n d s by a mi ni mum of 0.06 mm. the sol der resi st mi s-ali gnment i s a maximum of 0.05mm and i t is re comm e nded that the lead lan d s are all no n sol der mask defined (nsmd). theref ore pulling the s/r 0.06mm will al ways ensure nsmd pads. ? the minimu m solde r re si st width is 0.1 3 mm, therefore it is reco m m ende d that the sold er resist is co mplet e ly remove d fro m betwee n the lead lan d s f o rmin g a sin g l e openi ng for each ?group ? of lead land s. ? at the inside corne r of the sold er re sist whe r e the l e ad lan d grou ps me et, it is re comme nd ed to p r ovide a fillet so a solder resi st widt h of ? 0.17m m remain s. ? the la nd p a d sho u ld b e s o lder ma sk defined (smd), wi th a mi nimum ove r lap of the solde r re sist o n to t he cop per of 0.0 6 mm to acco mmodate sol der resi st mi s-align m ent. in 0.5mm pitch ca se s it is a llowa ble to ha ve the sold er resist openi ng fo r the land pa d to be smalle r than the part pad. ? ensu re that the sol d e r re si st in-b etwe en the lead lan d s and th e pad land is ? 0.1 5 mm due to t he high aspe ct ratio of the so lder resi st stri p sep a ra tin g the lead la nd s from the pad land. ? the 4 vias in the land pa d sho u ld be tented with so l der re si st 0.4mm diamet er, or 0.1mm larger tha n the diamete r of the via. page 3 3 of 35 1/31/05
ir3087pbf stencil de sign ? the sten cil apertu re s fo r the l ead la nds shoul d be a p p r oxim ately 80% of the are a of the l ead la nds. reduci ng the amount of solder deposit ed will minimi ze the occurrence of le ad shorts. since for 0.5mm pit c h device s th e l ead s a r e onl y 0.25mm wi de, the ste n cil ape rtures should not be made na rrower; o peni ngs in sten cils < 0.2 5 mm wid e are difficult to maintain repe atable solde r relea s e. ? the sten cil le ad land ap ert u re s sh ould t herefo r e b e shorten ed in l ength by 80 % and cente r ed on the lea d land. ? the la nd pad ape rture sho u ld b e stripe d with 0.25 m m wid e o peni ngs an d spa c es to de po sit app roximatel y 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lea d land s will be o pen. ? the maximu m length a n d width of the l and p ad ste n c il ap ertu re should b e eq u a l to the sol d er resi st ope n i ng minus an an nular 0.2mm pull ba ck to decrea s e the inci d e n c e of sho r ting th e cente r la nd t o the le ad la nds whe n the part is pushed int o the sold er p a ste. page 3 4 of 35 1/31/05
ir3087pbf package information 20l mlpq (4 x 4 mm body ) ? ja = 32 o c/w, jc = 3 o c/w data an d sp e c ificatio ns su bject to ch an ge witho u t no tice. this p r od uct has b een d e signed a nd qu alified for the con s um er m a rket. qualification standards ca n be found o n ir?s we b sit e . ir wo rl d h e adq u a r t ers: 233 kansas st., el segundo, calif orni a 90245, usa te l: (310) 252-7105 tac fax: (31 0 ) 252 -7 903 vis i t us at www.irf.c om for s a les contac t information . ww w.irf.co m page 35 of 3 5 1 /31/05

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